WEBVTT 00:01.480 --> 00:08.480 So, today we are going to talk about dopant redistribution during oxidation. That is you 01:15.430 --> 01:21.070 know that the silicon is doped either p-type or n-type, moderately or heavily as the case 01:21.070 --> 01:28.070 may be and when we carry out the oxidation, what happens to the impurity? So, that is 01:29.070 --> 01:35.540 called the dopant redistribution effect. In this context, first of all we will define 01:35.540 --> 01:41.700 a term called the segregation coefficient. Segregation coefficient is something, I think 01:41.700 --> 01:46.780 once before also we have mentioned. In this case, we are going to talk about the segregation 01:46.780 --> 01:53.780 of the dopant impurity, the relative segregation in silicon and in silicon dioxide. Which way 01:55.890 --> 02:02.890 the dopant moves? Does it preferentially go into the oxide or does it preferentially stay 02:03.310 --> 02:09.679 back in silicon? That is going to vary from impurity to impurity. 02:09.679 --> 02:16.679 So, in that context we will define a term called the segregation coefficient. This will 02:25.109 --> 02:32.109 be defined as the equilibrium concentration of dopant in silicon divided by the equilibrium 02:40.159 --> 02:45.030 concentration of the dopant in silicon dioxide. That is it is a ratio. 02:45.030 --> 02:52.030 This 03:16.780 --> 03:22.739 is defined as the equilibrium concentration of the dopant, equilibrium concentration of 03:22.739 --> 03:28.159 the dopant in silicon, it is the ratio of the equilibrium concentration of the dopant 03:28.159 --> 03:35.159 in silicon to the equilibrium concentration of the dopant in silicon dioxide. This ratio 03:35.480 --> 03:42.480 is called, usually the symbol is K or M. As this is a ratio, you can understand that its 03:48.920 --> 03:55.920 value can be either greater than 1 or less than 1. What do I mean? When K for example 03:57.129 --> 04:04.129 say is less than 1, that means the equilibrium concentration of the dopant is less in silicon 04:05.049 --> 04:12.049 compared to in silicon dioxide. If K is greater than 1 that means the equilibrium concentration 04:12.919 --> 04:19.190 of the dopant in silicon is greater than in case of silicon dioxide. 04:19.190 --> 04:26.190 Now, depending on these cases whether K is less than 1 or greater than 1, I may have 04:27.140 --> 04:33.500 different possibilities. In addition to this segregation coefficient, there is another 04:33.500 --> 04:40.500 factor to be considered. That is how fast the dopant can diffuse through oxide. Remember 04:44.200 --> 04:51.160 that we said one of the most desirable properties of silicon dioxide is that it can act as a 04:51.160 --> 04:58.160 mask against dopants. What do I mean? I mean that most of the normal dopants that we use 05:02.080 --> 05:09.080 for silicon, they do not diffuse through silicon dioxide as fast as they diffuse through silicon. 05:13.410 --> 05:20.370 That is the silicon dioxide blocks its movement, silicon dioxide acts as a mask. So, for these 05:20.370 --> 05:27.370 dopants we can consider that they diffuse slowly through the oxide and then there are 05:29.550 --> 05:36.550 some other impurity elements, for example gallium, which will diffuse very fast through 05:38.870 --> 05:45.680 silicon dioxide. That is a reason why gallium in spite of being a Group III element is not 05:45.680 --> 05:51.800 normally used as a p-type dopant in silicon, simply because silicon dioxide cannot block 05:51.800 --> 05:52.640 its movement. 05:52.640 --> 05:59.640 So, you see now I have two facts to concern, consider. One is the segregation coefficient 06:02.540 --> 06:09.540 and the other is whether the dopant diffuses fast or slow through silicon dioxide. Depending 06:11.280 --> 06:15.640 on that I can have a variety of situations. 06:15.640 --> 06:22.640 For example concentrate on figure a. The legend says K is less than 1. K, you know, is defined 06:29.740 --> 06:35.720 by the equilibrium concentration of the dopant in silicon divided by the equilibrium concentration 06:35.720 --> 06:42.550 of the dopant in silicon dioxide. That is less than 1 and I have also added rather cryptically 06:42.550 --> 06:49.370 a term called slow. That means the diffusion of this impurity through silicon dioxide is 06:49.370 --> 06:56.370 slow. An example is boron, boron in silicon. Boron has a segregation coefficient less than 06:58.270 --> 07:05.270 1 and boron is a slow diffuser through silicon dioxide. That is why we can use boron as a 07:06.450 --> 07:13.450 p-type dopant. So, what is the situation? Since K is less than 1 that means the dopant 07:17.290 --> 07:23.590 boron will preferentially go into silicon dioxide, because its equilibrium concentration 07:23.590 --> 07:27.500 is more in silicon dioxide than in silicon. 07:27.500 --> 07:34.500 You see, this line is the interface between silicon dioxide and silicon. At the interface, 07:35.720 --> 07:42.720 on the silicon side the boron concentration is less than on the silicon dioxide side. 07:43.310 --> 07:50.310 Do you see? In other words, at the silicon-silicon dioxide interface, there is a depletion of 07:54.510 --> 08:01.510 boron. Near the interface the boron concentration is less. Do you see that? This is because 08:03.750 --> 08:10.750 of the fact K is less than 1. Now, the boron profile inside the silicon dioxide. At the 08:14.170 --> 08:19.990 interface, this concentration should be higher on the oxide side that is because K is less 08:19.990 --> 08:26.290 than 1, equilibrium concentration of boron in silicon dioxide is high and then it will 08:26.290 --> 08:32.399 remain more or less constant over quite a distance inside the oxide that is because 08:32.399 --> 08:39.399 it is a slow diffuser in oxide, it cannot move very fast. Only towards the surface it 08:40.689 --> 08:47.689 starts to fall. Do you understand? This is when the segregation coefficient is less than 08:51.810 --> 08:57.339 1 and the diffusion of the dopant through the oxide is slow. 08:57.339 --> 09:04.339 Two facts you have to be very careful about. That is at the interface, on the silicon side 09:06.370 --> 09:11.660 the concentration is less, signifying K is less than 1. On the silicon side, the concentration 09:11.660 --> 09:18.660 of boron is less as shown by the red line. On the silicon dioxide side it is more and 09:19.970 --> 09:25.579 this concentration remains more or less constant over a considerable distance that is because 09:25.579 --> 09:32.579 the diffusion is slow and then towards the surface it starts to fall. Let us look at 09:33.660 --> 09:40.060 a variation of this thing. Let us consider that the segregation coefficient is still 09:40.060 --> 09:47.060 less than 1, but the dopant is a fast diffuser. It diffuses fast through the oxide. A practical 09:49.519 --> 09:56.519 example is again boron, but this time we will use a hydrogen ambient. If you use a hydrogen 09:58.189 --> 10:05.189 ambient, then boron can diffuse fast through silicon dioxide. That is why normal boron 10:05.850 --> 10:12.749 diffusion is never done in hydrogen ambient, but always in oxygen or nitrogen ambient. 10:12.749 --> 10:19.749 In hydrogen ambient, boron can diffuse fast through silicon dioxide. That is my case b. 10:21.319 --> 10:28.319 K is still less than 1, but now instead of slow, I am considering a fast diffuser through 10:29.290 --> 10:36.290 oxide. Again you see, if you look at the silicon-silicon dioxide interface, because K is less than 10:37.339 --> 10:44.339 1, on the silicon side the boron concentration is falling near the interface as shown by 10:45.759 --> 10:52.759 the red line and at the interface on the silicon dioxide side, I have a higher boron concentration. 10:53.990 --> 11:00.990 Do you see? This is because segregation coefficient K is less than 1, but because of the presence 11:04.389 --> 11:11.389 of hydrogen, now boron can diffuse fast through the oxide. That is why you see it is, the 11:12.410 --> 11:19.129 concentration is falling very fast. It is diffusing out through the oxide. That is the 11:19.129 --> 11:26.129 difference between these two pictures. In the first case when the diffusion was slow, 11:27.930 --> 11:32.850 you have seen that the boron concentration remains more or less constant in the oxide, 11:32.850 --> 11:38.620 only towards the surface it starts falling. Here you see however that it is diffusing 11:38.620 --> 11:42.350 fast out, right. 11:42.350 --> 11:49.350 Let us now consider a case where the segregation coefficient is greater than 1. A case is phosphorus. 11:56.759 --> 12:03.759 Phosphorus has a segregation coefficient of K greater than 1 and phosphorus is also a 12:04.100 --> 12:09.619 slow diffuser through oxide. It stands to reason because, phosphorus is a very common 12:09.619 --> 12:16.199 n-type dopant. It can be used because silicon dioxide can mask phosphorus, its diffusion 12:16.199 --> 12:20.399 through silicon dioxide is slow. In this case what will happen? 12:20.399 --> 12:27.399 Because K is greater than 1, you see on the silicon side, I see a pile up of phosphorus. 12:30.269 --> 12:37.269 That is at the interface the phosphorus is preferentially staying back in silicon. So, 12:39.610 --> 12:44.759 what you see here is that red line moving up. In these two figures what did you see? 12:44.759 --> 12:51.759 The red line was moving down. That is because K was less than 1. Now, it is moving up because 12:52.149 --> 12:59.149 K is greater than 1. It is commonly referred to as a pile up, pile up, phosphorus pile 12:59.230 --> 13:06.230 up. 13:07.470 --> 13:14.470 Phosphorus is piling up at the silicon-silicon dioxide interface. That is why on the silicon 13:18.360 --> 13:24.550 side I see the phosphorus pile up. On the silicon dioxide side, you notice that at the 13:24.550 --> 13:30.430 interface, the concentration of phosphorus is less on the silicon dioxide side. This 13:30.430 --> 13:37.430 black line starts at a level lower than the red line at the interface, right and phosphorus 13:40.259 --> 13:47.259 is a slow diffuser in the oxide. Therefore the profile of phosphorus in the oxide is 13:48.100 --> 13:55.100 also going to be somewhat similar to this. That is it stays more or less constant over 13:55.160 --> 14:00.980 a considerable distance and only towards the surface it starts falling. 14:00.980 --> 14:07.980 The important difference between a and c is in the silicon-silicon dioxide interface. 14:09.170 --> 14:16.170 In one case, the boron concentration at the interface is low on the silicon side. The 14:16.209 --> 14:21.869 phosphorus concentration at the silicon-silicon dioxide interface is high on the silicon side. 14:21.869 --> 14:28.869 That is because of the difference in the values of K, whereas the profile inside the silicon 14:30.149 --> 14:37.149 dioxide is dominated simply by the diffusion factor and since both of them are slow diffuser, 14:39.809 --> 14:46.809 look at these two profiles, they look more or less same inside the silicon dioxide, right. 14:51.189 --> 14:58.189 I now come to the final variation of the theme. That is K is greater than 1, but it is a fast 15:00.249 --> 15:06.249 diffuser. I have already given the example of gallium, gallium is an example of this. 15:06.249 --> 15:12.610 Gallium has a segregation coefficient greater than 1 and gallium is an extremely fast diffuser 15:12.610 --> 15:16.209 in the oxide. 15:16.209 --> 15:23.209 This figure however is a bit more confusing. You see, gallium has a segregation coefficient 15:24.009 --> 15:29.550 greater than 1. So, what should you have expected? You should have expected a pile up at the 15:29.550 --> 15:35.739 silicon-silicon dioxide interface, isn't it? In the phosphorus case, because K was greater 15:35.739 --> 15:40.389 than 1, you got a pile up. So, even in the case of gallium, it stands to reason that 15:40.389 --> 15:45.230 since K is greater than 1, I would expect a pile up of gallium at the silicon-silicon 15:45.230 --> 15:52.230 dioxide interface. Instead of that you see, if anything, it is falling. That is because, 15:52.929 --> 15:57.790 here the diffusion factor is going to dominate the phenomena. 15:57.790 --> 16:04.790 Gallium is an extremely fast diffuser. There is no chance for gallium to pile up at the 16:05.649 --> 16:12.649 interface, it just diffuses out. It just cannot pile up at the interface, it is forced out 16:15.660 --> 16:22.660 through the oxide. That is why you see, inside the oxide it just falls drastically, so sharply 16:23.509 --> 16:30.509 it is falling and even this effect continues even at the silicon-silicon dioxide interface. 16:32.269 --> 16:39.269 It just draws the gallium out from this region, so that if anything, actually the gallium 16:39.999 --> 16:46.769 concentration is a bit less at the silicon-silicon dioxide interface than inside the bulk. It 16:46.769 --> 16:53.769 does not get a chance to pile up, to build up. Now, in the light of these four cases, 16:58.209 --> 17:05.209 now let us see whether we can take a look once again to the oxide thickness problems 17:10.819 --> 17:17.819 on a heavily p-type and a heavily n-type silicon. That is to say, suppose I have a silicon wafer 17:19.519 --> 17:26.519 which is heavily phosphorus doped, n plus with phosphorus. 17:27.069 --> 17:34.069 The situation that you are expecting is case c, right. This silicon is heavily doped with 17:44.539 --> 17:50.649 phosphorus. So, at the interface, what do you expect? At the silicon-silicon dioxide 17:50.649 --> 17:57.649 interface, you expect a pile up of phosphorus. Now you remember, thermal oxidation is taking 17:59.269 --> 18:06.269 place inwards. That is oxide is going to be formed in this direction. So, it is this heavily 18:09.019 --> 18:16.019 phosphorus piled up region which is getting oxidized, agreed. This affects the reaction 18:17.090 --> 18:24.090 rate. You are modifying the quality of this region. This is the region where the oxidizing 18:26.070 --> 18:33.070 species are reacting with the silicon, so you are affecting the reaction rate. So, so 18:33.330 --> 18:40.330 long as the oxidation process is governed by the reaction rate, you can expect a thicker 18:42.750 --> 18:49.750 oxide growth. That is why you see that when the silicon wafer is heavily phosphorus doped 18:50.830 --> 18:57.830 the thicker or the faster oxide growth phenomena occurs at relatively lower temperature, where 18:59.899 --> 19:06.640 the reaction rate is dominating the process. 19:06.640 --> 19:13.640 In contrast, if I have a heavily boron doped p plus wafer, then the situation I expect 19:21.830 --> 19:28.830 is case a, right, oxidizing ambient. It is a slow diffuser. Remember, boron will be a 19:33.580 --> 19:36.970 fast diffuser only in hydrogen ambient. We are carrying out the oxidation, so you are 19:36.970 --> 19:43.970 working in oxidizing ambient. So, if the case is a, in this case, what do you see? Boron 19:44.789 --> 19:51.789 has preferentially come inside the oxide. So, this increased presence of boron in silicon 19:59.169 --> 20:06.169 dioxide is going to affect the diffusion of the oxidizing species through the oxide. It 20:09.260 --> 20:16.260 is going to aid in the diffusion of the oxidizing species, because now you have a silicon dioxide, 20:16.380 --> 20:23.380 which is heavily boron doped. That is why for a p plus silicon wafer, the faster oxide 20:30.460 --> 20:37.460 growth rate will continue at all temperature, because you are affecting the diffusion, right. 20:43.600 --> 20:50.600 This is the two cases for a p plus doped silicon and for a n plus doped silicon. In both cases, 20:53.570 --> 21:00.570 the growth rate will be affected, but for different reasons. When it is phosphorus doped, 21:00.799 --> 21:06.019 it is affected because the reaction rate is affected. When it is boron doped, it is affected 21:06.019 --> 21:13.019 because the diffusion is affected, right. 21:16.659 --> 21:23.659 So, now that we have talked about the oxidation, thermal oxidation of silicon in general, let 21:27.590 --> 21:34.590 us take a look at the practical oxidation systems. How do we oxidize a silicon wafer? 21:35.710 --> 21:41.019 As I have already told you, oxidizing a silicon wafer, thermally oxidizing a silicon wafer 21:41.019 --> 21:48.019 is a very simple process. What you do is you put the silicon wafers inside a furnace. Remember, 21:52.289 --> 21:59.289 contamination is always a key problem in all VLSI processing. Therefore, to avoid contamination, 22:01.029 --> 22:08.029 the furnaces, the tubes, the furnace tubes must be made of quartz. Quartz is silicon 22:08.220 --> 22:15.220 dioxide, so silicon dioxide will have the minimum source of contamination and even better 22:17.919 --> 22:24.919 idea will be to use pure silicon tubes, but that is very, very expensive. Very few places 22:26.519 --> 22:33.519 who really are bothered about the stringent quality of the oxide, they use the silicon 22:34.990 --> 22:39.610 furnaces, actually silicon furnaces. The furnaces are also made, furnace tubes are also made 22:39.610 --> 22:46.610 of silicon. But most commonly the furnace tubes are made of fused silica, quartz. 22:46.649 --> 22:53.649 So, you have, you see, two options. One is you pass pure oxygen through it. Oxidation 23:01.539 --> 23:08.539 is called the dry oxidation process or you can pass steam. A very common way of passing 23:11.320 --> 23:18.320 steam is you have a water bubbler. That is you have a quartz container containing deionized 23:20.639 --> 23:27.639 water. Remember, for VLSI processing, we always use deionized water to minimize contamination. 23:28.480 --> 23:35.480 So, you put deionized water and this container is placed in a heater, so that its temperature 23:37.760 --> 23:44.190 is just below the boiling point of water, just at or below the boiling point of water 23:44.190 --> 23:51.190 and you pass a stream of gas. That gas can be oxygen, it can also be nitrogen, it does 23:51.509 --> 23:57.490 not matter. That is because, your oxidizing species are going to be steamed, not oxygen 23:57.490 --> 24:04.000 and since the steam oxidation rate is much faster than the dry oxidation rate, it does 24:04.000 --> 24:08.769 not matter whether you are passing oxygen or nitrogen, because the oxidation rate will 24:08.769 --> 24:11.750 be determined by the steam oxidation rate alone. 24:11.750 --> 24:18.750 So, you bubble the gas through this container, so that the outlet is gas saturated with water 24:20.320 --> 24:27.320 vapour and that is now passed inside the furnace tube, in a quartz boat. We call it a boat 24:31.250 --> 24:37.980 that is a carrier which contains the wafers. So, inside this boat you place the wafers 24:37.980 --> 24:44.980 and put it inside the furnace where the requisite temperature is maintained. So, in presence 24:45.399 --> 24:52.399 of oxygen or in presence of this gas saturated with water vapour, oxide is formed on silicon. 24:56.909 --> 25:03.909 Usually, if you are going to grow a thick oxide, that is for masking purposes, thick 25:05.500 --> 25:12.500 oxide that is say, 5000 Angstrom or 6000 Angstrom or thicker than that, then we use a dry wet 25:13.509 --> 25:20.509 dry sequence. That is first 10 minutes you carry out dry oxidation, then you carry out 25:21.789 --> 25:28.080 wet oxidation, for whatever time duration, then you follow it up again with a dry oxidation. 25:28.080 --> 25:35.080 The idea is to have the interface of a good quality. That is why the final dry oxidation. 25:37.250 --> 25:44.250 Then, you get your requisite thickness and you take it out. There is another possibility. 25:48.509 --> 25:55.509 In some systems instead of using the water bubbler arrangement, you directly introduce 25:56.139 --> 26:03.139 hydrogen and oxygen in the system where they form steam. 26:03.840 --> 26:10.840 This is called pyrogenic oxidation system, pyrogenic water system or pyrogenic oxidation 26:11.130 --> 26:18.130 system, where hydrogen and oxygen - a mixture is introduced and it forms water inside the 26:51.039 --> 26:58.039 system and this reacts with the wafer to form the oxide. As I have already mentioned, dry 27:05.120 --> 27:12.120 oxide has greater density and better quality. What exactly I mean by better quality, we 27:14.210 --> 27:21.210 will come to, a little later. Wet oxidation on the other hand is thicker oxide and is 27:21.529 --> 27:28.529 used for masking or isolation. Now, there are a few variations of the theme. 27:30.000 --> 27:37.000 First of all, let us say I want to grow a very, very thick oxide. That means I have 27:42.659 --> 27:49.659 to either increase the temperature or increase the time of oxidation, agreed. Now, whenever 27:55.139 --> 28:01.190 you are doing either of these two, normally the oxidation temperatures are say, from 900 28:01.190 --> 28:07.700 degree centigrade to 1200 degree centigrade, depending on what you want. These are the 28:07.700 --> 28:13.600 normal range of temperature for oxidation. It can be a little less, it can be 800 also, 28:13.600 --> 28:20.460 but normal range is 900 to 1200 degree centigrade. Now, if you want to grow very thick oxide 28:20.460 --> 28:27.460 that means the wafers have to be subjected to very high temperature for a prolonged duration. 28:29.210 --> 28:36.210 This causes a lot of stress on the wafer. Also, the oxide that is formed, it is amorphous. 28:40.340 --> 28:45.480 This is what we want, amorphous silicon dioxide. 28:45.480 --> 28:52.480 On prolonged exposure to high temperature, this amorphous oxide can get devitrified, 28:55.840 --> 29:02.840 devitrification or devitrified. Whenever we want to grow very thick oxide that means we 29:17.509 --> 29:24.129 have to carry out wet oxidation at very high temperature, for very long time and then devitrification 29:24.129 --> 29:30.029 occurs. What is devitrification? Instead of this amorphous silicon dioxide, we get poor 29:30.029 --> 29:37.029 quality crystalline silicon dioxide and that is no good. That will not serve either for 29:40.980 --> 29:47.980 masking or for isolation. It will just be poor quality crystalline silicon dioxide with 29:50.679 --> 29:57.679 a lot of cracks, lot of defects and that will not serve either as a good mask or for isolation. 30:02.360 --> 30:09.360 So, what is the way out? How do we grow good, thick oxide? By thick oxide I mean more than 30:15.059 --> 30:22.059 1 micron. Normal wet oxidation, the limit is approximately at 1micron, beyond that it 30:25.769 --> 30:32.769 tends to devitrify. How do we grow good quality thicker oxide? That is one of the challenges 30:37.330 --> 30:44.330 which was posed to the VLSI processing technologists. I have to ask you to take another look at 30:52.950 --> 30:59.870 the oxidation rate constants. We have defined two rate constants, remember. The linear rate 30:59.870 --> 31:05.529 constant and the parabolic rate constant. 31:05.529 --> 31:12.529 The parabolic rate constant B was 2 D C star by N 1 and A was ........, isn't it. So, you 31:37.210 --> 31:44.210 know, B by A will be C star by N 1 into 1 by K S plus 1 upon h, right. This C star that 31:59.860 --> 32:06.860 is the equilibrium concentration of the oxidizing species in the oxide, this is proportional 32:08.889 --> 32:13.159 to pressure. 32:13.159 --> 32:20.159 This varies with pressure, gas pressure. So, if you raise the pressure, if you carry out 32:34.600 --> 32:41.600 oxidation under high pressure, you are going to increase both B as well as B by A. Both 32:44.879 --> 32:51.879 the linear and parabolic rate constants are going to increase. So, this is something which 32:55.789 --> 33:02.789 is done. It has a number of interesting fallouts. First of all, your problem of growing thicker 33:03.749 --> 33:10.749 oxide is now solved, right. You have increased both the linear and the parabolic rate constants. 33:12.740 --> 33:19.659 Therefore, at the same temperature and in comparable time, compared to the atmospheric 33:19.659 --> 33:26.659 pressure oxidation, you can now grow a much thicker oxide without the fear of devitrification, 33:27.879 --> 33:34.679 because you are not subjecting for any longer duration or at any higher temperature. That 33:34.679 --> 33:36.259 is one possibility. 33:36.259 --> 33:43.259 The other possibility is suppose I do not have to grow such thick oxide, it will do 33:43.720 --> 33:49.990 to grow even 5000 Angstrom, I have now one more parameter to play with. By increasing 33:49.990 --> 33:56.990 the pressure, I can cut down either on temperature or on time and grow comparable thicknesses. 34:00.509 --> 34:07.509 Do you understand? Previously, I had only two parameters to play with, temperature and 34:08.379 --> 34:14.409 time. Now, I have a third parameter, pressure. By increasing the pressure, I can now afford 34:14.409 --> 34:21.139 to cut down either the temperature or the time. What are the advantages? If I can cut 34:21.139 --> 34:27.970 down the time, my throughput increases, right. For the same oxidation which previously needed 34:27.970 --> 34:32.879 1 hour, I can probably finish it in half an hour. That means instead of 1 run, I can now 34:32.879 --> 34:36.740 have 2 runs, throughput is doubled. 34:36.740 --> 34:43.740 Alternately, let us keep the time same, I have cut down the temperature; so, my thermal 34:44.730 --> 34:50.030 budget is reduced. It costs money to run the furnaces, to raise the furnace temperature. 34:50.030 --> 34:57.030 They are all electrically heated. Electricity costs a lot of money and also your wafers 34:58.740 --> 35:05.740 are now not being subjected to as much thermal stress. The thermal stress is becoming less 35:06.010 --> 35:13.010 and you take it from me, the thermal stress problem is getting more and more serious as 35:13.089 --> 35:18.800 we increase the diameter of the wafer, because you see the wafer thickness is not really 35:18.800 --> 35:25.069 increasing at a proportional rate. For 2 inch wafers, the thickness used to be, may be 300 35:25.069 --> 35:32.069 odd microns. Now even for a six inch wafer, it is say, about 500 microns. So, it is not 35:33.510 --> 35:39.920 really increasing at a proportional rate. That means the wafer now is more prone to 35:39.920 --> 35:41.309 thermal warping. 35:41.309 --> 35:48.309 Warping means it bends, it buckles at high temperature. So, by cutting down the temperature, 35:51.800 --> 35:58.800 you can let your wafers stay more healthy. They are not subjected to as much thermal 35:59.010 --> 36:03.510 stress. At the same time, you are cutting down your thermal budget. So, you are saving 36:03.510 --> 36:10.260 a lot of money and believe me, engineering is all about saving money. Your product must 36:10.260 --> 36:15.859 be cheaper than others product, only then you can sell. So finally, that is the bottom 36:15.859 --> 36:18.099 line, the cost is the bottom line. 36:18.099 --> 36:25.099 So, high pressure oxidation in both senses, in more sense than one, it offers interesting 36:25.260 --> 36:32.260 possibilities. You can grow thicker oxide, you can also grow normal oxide at a reduced 36:33.950 --> 36:40.950 thermal budget or at a reduced time. So, high pressure oxidation is a very interesting proposition 36:42.400 --> 36:49.170 today and in our lab, we have one high pressure oxidation system. It is most probably the 36:49.170 --> 36:55.420 only one in India and this is indigenously developed. It is developed in our lab, by 36:55.420 --> 37:01.829 our people in our lab and high pressure oxidation system is available. So, sometime I will take 37:01.829 --> 37:08.829 you to the lab and let you have a look at this. I said I will talk about the quality 37:15.410 --> 37:22.410 of the oxide. How to, I said that dry oxidation will give you better quality oxide compared 37:24.290 --> 37:31.290 to wet oxidation. Now, exactly what do I mean by the quality of oxide? 37:32.410 --> 37:39.410 I have a card here, which outlines some of the non idealities inside the oxide. See, 37:47.930 --> 37:53.650 the silicon dioxide, ideally it should be an insulator. There should be no charge in 37:53.650 --> 38:00.650 this, it should be an insulator with a perfect interface between the silicon and silicon 38:00.670 --> 38:06.839 dioxide. Although silicon dioxide does fulfill a lot of these requirements, there is still 38:06.839 --> 38:13.839 some non idealities and the most important way of visualizing what the oxide quality 38:19.280 --> 38:26.000 is, is by identifying the charges that are present in the oxide, because they represent 38:26.000 --> 38:33.000 the non idealities. So, in this card I have schematically represented the various types 38:34.520 --> 38:40.099 of charges and where these charges are located. 38:40.099 --> 38:47.099 First of all, note this red line. Red is danger, red also means very important, right. So, 38:50.170 --> 38:57.170 this is my very important line, demarcation line that is the line between silicon and 38:57.950 --> 39:04.950 silicon dioxide. It is the interface, silicon and silicon dioxide interface. Now, this interface 39:07.140 --> 39:14.140 is going to dictate a lot of the things, particularly in relation to a MOSFET. There are non idealities 39:21.680 --> 39:28.680 present in the interface called the interface trapped charges. These interface trapped charges 39:32.900 --> 39:38.540 may come about because of various things. It can be because of some mechanical damages 39:38.540 --> 39:44.910 already present in the wafer, it can be because of some broken bonds, broken silicon bonds, 39:44.910 --> 39:51.910 it can be because of various things. So, this is one major source of non idealities and 39:53.890 --> 40:00.410 it adversely affects the MOS device characteristics. 40:00.410 --> 40:07.099 As the name itself suggests, it is present right at the silicon-silicon dioxide interface 40:07.099 --> 40:14.099 and is generally represented, if you look at the energy band diagram, this is your silicon 40:19.670 --> 40:26.670 dioxide. It is generally represented as states present all over the forbidden energy gap. 40:31.309 --> 40:37.260 These are available energy states present all over the forbidden energy gap. They can 40:37.260 --> 40:44.260 trap and detrap electrons that is it takes part in the electronic activity. So, this 40:48.390 --> 40:55.390 is one major non ideality. The other major non ideality is a little distance away from 40:57.380 --> 41:04.380 the interface in the oxide. This distance is about 100 Angstrom or so, marked with green 41:08.220 --> 41:15.220 and you will notice I have put only positive signs there. That is because in silicon thermal 41:16.720 --> 41:23.720 oxidation, these charges are mostly always only positive charges and they come about 41:27.780 --> 41:34.780 because of incomplete oxidation. Again remember, thermal oxidation is taking place inwards. 41:35.140 --> 41:39.920 That is the interface is the region which is oxidized the last. 41:39.920 --> 41:46.599 Now think of a practical process. Towards the end of the oxidation you are going to 41:46.599 --> 41:53.599 switch off the gas supply. So, chances are that is where the oxidation process is going 41:55.299 --> 42:02.299 to be incomplete. You are reducing the oxidant species supply. So, chances are this is where 42:04.660 --> 42:11.660 the oxidation is going to be incomplete. That is why here the composition of the oxide will 42:13.660 --> 42:20.660 not be exactly SiO 2, but it will be SiO x, x being less than 2. I have less oxygen in 42:24.099 --> 42:31.099 silicon dioxide. This automatically means that I have more positive charges, isn't it. 42:41.490 --> 42:48.490 That is why this fixed oxide charges are almost always, they are only positive in nature. 42:56.049 --> 43:03.049 The term fixed oxide charge obviously signifies that these charges are fixed. They cannot 43:03.099 --> 43:09.750 move about, they cannot be decharged or discharged. 43:09.750 --> 43:16.750 So, this is the second major non ideality and this fixed oxide charge also affects the 43:17.530 --> 43:24.530 threshold voltage of a MOS device. Because they are positive, they will push the threshold 43:29.099 --> 43:36.099 voltage of a MOS device into the negative detection. That is now you first have to apply 43:36.960 --> 43:43.960 a gate voltage in order to neutralize these positive charges, so as to get back the ideal 43:44.960 --> 43:51.960 condition, so that much extra negative voltage is added to the actual threshold voltage of 43:52.579 --> 43:58.480 the MOS device. That is why we say that if the fixed oxide charge is present, it pushes 43:58.480 --> 44:05.480 the threshold voltage to the negative detection and then, all over the oxide I may have this 44:10.309 --> 44:17.309 orange marks which are called oxide trapped charges. That is these are the charges trapped 44:18.500 --> 44:20.329 in the oxide. 44:20.329 --> 44:26.930 How did these charges come about? There are a variety of sources. One source is suppose 44:26.930 --> 44:33.930 your device is exposed to radiation environment, then hole, electron pairs will be generated. 44:35.510 --> 44:42.510 Holes are relatively slow, therefore they will get trapped in the oxide. Other possibility 44:43.099 --> 44:50.099 is avalanche injection. Suppose you have a MOSFET with a very short channel. That means 44:50.849 --> 44:57.380 as the channel length is shorter, the electric field inside the channel is that much higher. 44:57.380 --> 45:04.380 So now, your electrons moving in the channel may have acquired sufficient energy to surmount 45:06.450 --> 45:13.450 the oxide silicon barrier and get injected into the oxide. Incidentally it is also called 45:17.150 --> 45:21.490 hot electron effect. The electrons are hot, they have acquired a lot of energy. Energy 45:21.490 --> 45:28.309 is equivalent to temperature, right. That means the electrons are hot, so they can have 45:28.309 --> 45:34.430 enough energy to surmount the barrier and get injected into the silicon dioxide. So, 45:34.430 --> 45:40.910 there are a variety of reasons, variety of sources by which these oxide trapped charges 45:40.910 --> 45:47.140 may occur. Most important are these two which I just outlined. One is if you are exposing 45:47.140 --> 45:52.210 your device to a radiation environment, the other is if avalanche injection is taking 45:52.210 --> 45:59.210 place and then finally I have what are called the mobile ionic charges. 46:01.930 --> 46:08.930 I have mentioned the two most important mobile ions, sodium and potassium and you know what 46:10.670 --> 46:17.670 are the greatest sources of this sodium and potassium. We humans; you have to handle your 46:19.500 --> 46:26.500 wafer and if you are not careful, from human body, the sodium and potassium ions can get 46:29.530 --> 46:36.530 into the oxide. Its another major source is water. Unless your water is properly deionized, 46:37.099 --> 46:42.220 they contain a lot of dissolved sodium and potassium salts. That means a lot of sodium 46:42.220 --> 46:49.220 and potassium ions and they are mobile. They play havoc with the system. They can move 46:49.750 --> 46:56.750 all the way from the silicon dioxide surface to the silicon-silicon dioxide interface, 46:58.260 --> 47:00.430 depending on the detection of the electric field. 47:00.430 --> 47:06.280 See, they are positively charged, sodium and potassium. So, suppose on top of this you 47:06.280 --> 47:11.390 have your metal gate that will be a MOS structure, right, metal oxide and semi conductor. Now 47:11.390 --> 47:17.930 suppose you apply a gate voltage, positive gate voltage. All these mobile ions will get 47:17.930 --> 47:23.910 pushed to the interface and suppose we apply a negative gate voltage, all these mobile 47:23.910 --> 47:30.910 ions will move up towards the surface. They are free to move. This check, whether mobile 47:35.730 --> 47:41.349 ions are present or not, it can be done very simply by doing a proper CV analysis, capacitance 47:41.349 --> 47:48.349 voltage analysis. It is a routine check in all fab labs, which make MOS devices. 47:49.450 --> 47:54.640 If you have sodium ions or potassium ions, might as well close down the lab, get rid 47:54.640 --> 47:59.150 of your sodium and potassium ions, because if they are present, none of your devices 47:59.150 --> 48:06.150 are going to work. So, it is a routine check. You must first get rid of sodium and potassium 48:08.299 --> 48:14.549 ions. Well, there are various ways and means of getting rid of this sodium and potassium 48:14.549 --> 48:21.549 ions. First cardinal rule is your system must be clean. If there are sodium or potassium 48:23.599 --> 48:30.599 ions, mobile ions present in your system, it says very badly about the cleanliness of 48:31.700 --> 48:38.700 your system. It says that your system is not clean enough. So, first of all you have to 48:40.230 --> 48:47.230 tighten the cleanliness of the system and there are also various other ways of getting 48:48.200 --> 48:55.200 rid of these mobile ions. One of them is called chlorine oxidation. 48:56.349 --> 49:03.349 In the next class, we will talk about ways and means of getting rid of these unwanted 49:04.170 --> 49:11.170 oxide charges, mobile ionic charges as well as the fixed oxide charges and the interface 49:11.710 --> 49:18.039 charges. The oxide trap charges, most often they are not really related to processing. 49:18.039 --> 49:24.349 They are most often encountered when your device is fabricated and after that it is 49:24.349 --> 49:29.450 being exposed either to radiation environment or your MOS device is being operated under 49:29.450 --> 49:36.450 very high channel electric field. So, they are not really so much related to the processing 49:36.589 --> 49:42.890 conditions, but the other three are - mobile ionic charges, fixed oxide charges and interface 49:42.890 --> 49:49.030 charges. So, in the next class we will talk about how to get rid of these charges. That 49:49.030 --> 49:54.420 is very important when you want to talk about the gate oxide in a MOS device.