WEBVTT 00:22.000 --> 00:29.000 So, we have been discussing about the basic I-square L circuit that is the integrated 01:33.850 --> 01:40.720 injection logic, in which we use both pnp and npn transistor. The pnp transistor is 01:40.720 --> 01:47.080 used as the current source. We use a lateral pnp for this application and we have an npn 01:47.080 --> 01:54.080 transistor, we use a vertical npn transistor. The difference in this I-square L npn transistor 01:54.670 --> 02:01.670 is that it is operating in an inverted mode. That is at the top surface we have the collector 02:01.990 --> 02:08.440 and the substrate is the emitter. So, this npn transistor is operating in an inverted 02:08.440 --> 02:14.010 mode and we have already seen that we can either add an n plus collar to this I-square 02:14.010 --> 02:21.010 L circuit, if we want to facilitate hole injection in the direction of the npn transistor and 02:22.040 --> 02:28.510 we can replace this n plus collar with an oxide isolation also. The oxide isolation 02:28.510 --> 02:35.510 will have the advantage of space saving, but at the same time we have to provide multiple 02:35.650 --> 02:40.340 base contacts if we want to avoid the problem of the unequal drives. 02:40.340 --> 02:47.340 So, with this background, let us now concentrate on a more advanced I-square L technology, 02:47.980 --> 02:54.980 where we use oxide isolation, yes; we use multiple base contacts, yes and we align the 02:58.640 --> 03:05.030 base contacts automatically. Thus the name self-aligned process; we have a self-aligned 03:05.030 --> 03:12.030 process, whereby the base contacts are aligned automatically with respect to the n plus collectors 03:13.930 --> 03:20.930 and we will see that in doing so, in developing this self-aligned I-square L technology, we 03:23.819 --> 03:30.819 take the help of various sophisticated technological steps, for example ion implantation, for example 03:31.300 --> 03:38.300 dry etching, for example chemical vapour deposition. So, this advanced self-aligned I-square L 03:39.769 --> 03:46.769 technology is possible or was first made possible because of the advent of these technologies. 03:47.190 --> 03:54.190 Let us now take a look at this self-aligned I-square L structure. 03:54.530 --> 04:01.530 You know that in the I-square L structure, we started off with the n on n plus substrate. 04:06.959 --> 04:13.959 This is permanently grounded and we have 04:21.400 --> 04:28.400 oxide isolation. The devices will be housed here, so we will have a p region here and 04:28.880 --> 04:35.880 another p region here, right. This is going to be my pnp transistor and in here I will 04:41.360 --> 04:48.360 diffuse in and we will have the npn transistor. Now, in the self-aligned I-square L technology 04:50.330 --> 04:57.330 also, up to this the process steps are exactly similar, exactly the same. 04:58.440 --> 05:05.440 So, what we have is ..... Then, we grow a thin oxide over this. This is thinner than 05:38.940 --> 05:45.940 this oxide, but it is not very thin; it is thick enough to mask. In the next step, we 05:56.210 --> 06:03.210 deposit; we do not dope, we do not diffuse, we deposit arsenic doped polysilicon over 06:06.970 --> 06:13.970 the p-type region topped with CVD silicon dioxide and pattern it. That is to say I have actually 06:42.120 --> 06:49.120 skipped one intermediate step. You first deposit this arsenic doped 07:00.039 --> 07:07.039 poly all over the region, then you top it up with CVD SiO 2 and then you pattern it, so that 07:14.430 --> 07:21.430 it is retained only over these regions. So, this arsenic doped poly is going to act as 07:32.860 --> 07:36.889 the collectors of the npn transistor. 07:36.889 --> 07:43.889 Now, you see, my next job is going to be to find out where I should put my base contacts. 07:46.740 --> 07:51.810 You know that I should have multiple base contacts that is I should have one base contact 07:51.810 --> 07:58.810 here, one base contact here, like that, yes; at the same time, you know that the base contact 07:59.849 --> 08:06.849 should not be in touch with the collector, should not be in touch with the collector, 08:08.030 --> 08:15.030 it will short. In that case, I will have the base collector short. So, I must put the base 08:22.550 --> 08:29.550 contacts properly. How do I do that? In doing this, we take the help of another CVD layer 08:32.870 --> 08:39.870 of silicon dioxide that is to say we deposit another silicon dioxide layer by chemical 08:52.290 --> 08:59.290 vapour deposition. 09:15.700 --> 09:22.700 So, I have two layers of CVD SiO 2. The first CVD layer was put on top of the arsenic doped 09:36.580 --> 09:43.580 poly and patterned, so that only the poly region has a cap of CVD SiO 2. In the next 09:43.690 --> 09:50.690 step, I have deposited another layer of CVD SiO 2 all over the place, right; fine. Now, 09:53.440 --> 10:00.440 my next step is to anisotropically etch part of this CVD SiO 2 layer. When I say anisotropically 10:06.330 --> 10:12.580 etch, I mean that the etching is only going to be in this direction, in the vertical direction. 10:12.580 --> 10:19.580 I can do that by using the dry etching technique, by suitably adjusting the etching conditions 10:22.350 --> 10:29.350 and I partly etch that is I etch only this much. So, what is going to happen? This is 10:43.050 --> 10:50.050 going to be removed from all these portions, but going to be retained at the side walls 11:04.510 --> 11:11.510 and at the top. So, you see, now, in addition to having the top capping layer of CVD SiO 11:57.120 --> 12:04.120 2, I have also added a side wall of CVD SiO 2 to my n plus poly regions, agreed. Now, 12:08.760 --> 12:15.760 all I have to do is to deposit the metal, aluminium, right and I etch this aluminium, 12:57.010 --> 13:04.010 this is a non-critical etching, from certain regions. 13:36.339 --> 13:43.339 So, you see, in one shot you have provided all the base contacts, multiple base contacts, 14:02.680 --> 14:09.680 right. So, this is the self-aligned I-square L technology, in which you make use of the 14:19.019 --> 14:25.470 more advanced etching technology that is the dry etching, the anisotropic etching, whereby 14:25.470 --> 14:32.470 you retain the side walls of CVD SiO 2 and remove silicon dioxide from everywhere else 14:34.480 --> 14:41.480 and this side walls of silicon dioxide actually provides the self-aligned technique, right. 14:42.130 --> 14:49.130 It protects the collector regions from getting shorted with the base metal contact. So, this 14:51.699 --> 14:55.970 is the self-aligned I-square L technology. 14:55.970 --> 15:02.970 You know, I told you previously that all the transistors we have discussed so far, the 15:08.449 --> 15:15.449 bipolar junction transistors, they are, so to speak, more or less general transistors, 15:16.260 --> 15:22.930 general npn transistors. We have not been very specific as to what their performances 15:22.930 --> 15:29.930 are. I-square L of course is a different story; because of its particular circuit configuration, 15:30.940 --> 15:37.940 you need to realize both a pnp and npn transistor and it is a merged transistor logic. So, we 15:38.889 --> 15:45.889 have discussed the particular building block of an I-square L in detail. But, nowadays 15:48.529 --> 15:55.529 as we are going for faster and faster circuits, you know bipolar junction transistors are 15:58.269 --> 16:03.899 faster circuits compared to MOS. We say that bipolar junction transistors are high speed 16:03.899 --> 16:10.389 and MOS are high density. So, when we are going for high speed transistors, we talk 16:10.389 --> 16:15.870 about bipolar junction transistors. We use bipolar junction transistors in ECL, emitter 16:15.870 --> 16:20.040 coupled logic. These are the fastest circuits. 16:20.040 --> 16:27.040 Now, when I want to have such a high speed transistor, what are the specific requirements 16:30.310 --> 16:37.310 of these transistors? Specific requirements of this transistor will be, first of all we 16:39.420 --> 16:46.420 must have a low base resistance. What do I mean that we must have a low base resistance? 16:46.709 --> 16:53.709 That means the extrinsic base must be highly doped and the extrinsic base must be aligned 16:54.490 --> 16:55.670 to the emitter. 16:55.670 --> 17:02.670 That is to say, if this is the base and this is the emitter, this is the base; your active 17:10.659 --> 17:17.659 transistor is here. So, this base doping is automatically fixed by the gain of the transistor, 17:19.630 --> 17:26.140 but you want to make these regions highly doped which are extrinsic base. At the same 17:26.140 --> 17:32.090 time, notice that the extrinsic base must be separated from the emitter, otherwise we 17:32.090 --> 17:39.090 will have an n plus p plus junction there, right. So, again you see, you need to have 17:41.380 --> 17:48.380 the extrinsic base self-aligned to the emitter. So, for high speed transistor, one of the 17:50.880 --> 17:57.880 major requirements is to have the extrinsic base self-aligned to emitter and of course, 17:59.500 --> 18:06.500 for any high speed circuits, you must have low capacitances, right; low collector base 18:08.809 --> 18:15.809 junction capacitance, low emitter base junction capacitance and if I want to have low emitter 18:16.299 --> 18:23.299 base junction capacitance, it is found that as the device dimensions become smaller, as 18:24.760 --> 18:31.760 the emitter size gets reduced, okay, let me redraw this. 18:38.980 --> 18:45.980 This is emitter, this is base. You see, the emitter base junction capacitance will have 18:49.750 --> 18:56.750 two parts. One is the planar capacitance that is determined by the size, the length of the 18:57.770 --> 19:04.770 emitter and the other is the peripheral or the side wall capacitance. So, the emitter 19:09.600 --> 19:12.610 base junction capacitance will have two parts. 19:12.610 --> 19:19.610 One is the planar part and the other is the side wall or the peripheral part and as we 19:20.610 --> 19:27.610 reduce the emitter dimensions, you see, increasingly the peripheral capacitance or the side wall 19:35.440 --> 19:42.440 capacitance become the dominating factor. As the emitter size reduces, the speed does 19:45.590 --> 19:52.570 not really become increased to that extent, because now, the peripheral capacitance is 19:52.570 --> 19:58.799 dominating instead of the planar capacitance and you have not done anything to the peripheral 19:58.799 --> 20:05.669 capacitance. How can you reduce the peripheral capacitance? By making the junctions shallower; 20:05.669 --> 20:12.669 not just reducing the emitter size, but also reducing the junction depth. So, for high 20:16.500 --> 20:23.230 speed transistors, it is very important that you have shallow junctions in addition to 20:23.230 --> 20:30.230 having smaller dimension. 20:33.220 --> 20:40.220 I just wanted to give you some example; for example, if the emitter area in micrometer 20:42.590 --> 20:49.590 square is 1.5 into 1.5 and if the junction depth, the emitter base junction depth, if 20:54.260 --> 21:01.260 that is 0.2 micron, then you have C planar and C side wall, let me call it C p and C 21:11.650 --> 21:18.650 s, C planar and C side wall, then these two are, okay, C planar is 4.1 and this is 3.0 21:27.210 --> 21:34.210 in femto farads, 10 power minus 15 farads femto farads; one is 4.1 femto farads and 21:34.240 --> 21:41.240 C s that is the side wall or the peripheral capacitance is 3 femto farads. On the other 21:44.330 --> 21:51.330 hand, if I reduce the emitter area to 0.5 into 0.5 and keep the junction depth the same 21:55.350 --> 22:02.350 as 0.2, then planar capacitance goes down to 0.46 femto farads, but the side wall capacitance 22:09.320 --> 22:16.320 is about 1 femto farads. So, you see, as you reduce the emitter size, for the same junction 22:19.070 --> 22:26.070 depth the side wall capacitance starts to dominate, when the emitter size is smaller. 22:28.150 --> 22:35.150 If we go for shallower junctions, like if we make it 0.02, nothing happens to the planar 22:45.130 --> 22:52.130 value of the capacitance, but this reduces and here also. So, you see, this becomes very 23:17.950 --> 23:24.950 important when the emitter size is reduced. For smaller device dimensions, it is very 23:27.159 --> 23:34.159 important that not merely you reduce the device dimensions, because that is finally not going 23:34.260 --> 23:39.690 to determine the speed, it is the peripheral capacitance or the side wall capacitance and 23:39.690 --> 23:46.690 that can be reduced only if you reduce the junction depth, which brings us to the important 23:47.530 --> 23:54.530 requirement of a high speed transistor - I must have shallow junctions. But you see, 23:57.610 --> 24:04.610 we have already stated that it is technologically difficult to realize shallow junctions; technologically 24:06.340 --> 24:10.970 it is going to be difficult. The shallower the junction is technologically if you ..... to 24:10.970 --> 24:16.840 diffusion or implantation, it is going to be difficult. The other point is from the 24:16.840 --> 24:18.450 transistor performance itself. 24:18.450 --> 24:25.450 Suppose I have emitter and the base and here I have certain p concentration, then it must 24:44.440 --> 24:51.440 fall to zero and it is almost a linear fall and the slope of this line determines the 24:58.400 --> 25:05.400 gain of the transistor. Now, if I have a shallower emitter base junction that is if I have a 25:09.470 --> 25:16.470 smaller emitter region, I have the same hole concentration and now it must go to zero here. 25:27.650 --> 25:34.419 That means I have a steeper slope if I want to have a narrower emitter, if I want to have 25:34.419 --> 25:41.419 a shallower emitter base junction and if I have a steeper slope that means the gain of 25:42.059 --> 25:49.059 the transistor is going to fall. So, if I want to have very shallow junctions, the gain 25:49.360 --> 25:56.360 of the transistor is going to be affected adversely. So, apart from the technological 25:56.760 --> 26:02.830 difficulty, it is also going to be detrimental to the transistor performance if we want to 26:02.830 --> 26:05.700 have a shallow emitter base junction. 26:05.700 --> 26:12.700 So, what we do is this. We use a poly emitter transistor; we use a poly emitter transistor. 26:14.710 --> 26:20.409 What is the significant of having a poly emitter transistor? That is you have, you deposit 26:20.409 --> 26:27.409 a poly layer; you implant it n plus and from that n plus you have, by thermal anneal you 26:28.970 --> 26:35.230 have a shallow junction. So, your emitter basically has two parts. One is in the poly, 26:35.230 --> 26:41.440 the other is the shallow doped region in the crystalline silicon. Now, what is the situation 26:41.440 --> 26:48.440 going to be? 26:49.850 --> 26:56.850 I have realized a shallow emitter junction, but I have an emitter in poly too. So, my 27:02.600 --> 27:09.600 emitter basically is having two parts - emitter in the crystalline silicon and emitter in 27:11.150 --> 27:18.150 the polysilicon. Now, if you want to look at how the hole concentration should fall, 27:21.640 --> 27:28.640 you know, it should actually does not have to go to zero here; it can come like this 27:29.039 --> 27:36.039 and then fall like this. I can keep the poly layer as thick as I want; does not matter, 27:38.650 --> 27:45.279 because it is not going to affect my peripheral capacitance at all. The peripheral capacitance 27:45.279 --> 27:52.279 will be determined only by the junction depth which is the depth of E C. That means what 27:54.600 --> 27:56.850 I am trying to say is this. 27:56.850 --> 28:03.850 I have the p region here for the base and I have deposited a poly here from which ..... So, 28:13.549 --> 28:19.289 the side wall capacitance is only determined by this region which is very shallow, but 28:19.289 --> 28:26.289 the entire region is working as my emitter and therefore, the slope of this curve does 28:27.020 --> 28:34.020 not have to be very steep; it does not affect the gain of the transistor. In fact, in poly 28:34.649 --> 28:41.649 emitter transistor the gain is increased. The poly emitter transistors have a lot of 28:46.559 --> 28:53.559 gain and the gain will be even more improved. Basically the gain improves because, hole 28:56.919 --> 29:03.919 injection is suppressed in this poly and crystalline interface and it can be further suppressed 29:04.230 --> 29:10.409 if you put a thin interfacial region here, thin oxide region here, thin interfacial oxide, 29:10.409 --> 29:17.279 then the injection of holes will be suppressed to a larger extent. The gain of transistor 29:17.279 --> 29:22.390 will become much higher. 29:22.390 --> 29:29.390 Now the point is, so we have underlined the basic strategy. What are our requirements? 29:33.240 --> 29:40.240 First of all, the extrinsic base must be self-aligned to the emitter and the other thing is that, 29:40.510 --> 29:47.350 in order to realize a shallow emitter without having to sacrifice the gain of the transistor, 29:47.350 --> 29:54.350 we must use a poly emitter. So, this is the strategy behind a high speed transistor in 29:56.200 --> 30:02.640 integrated circuit; high speed transistor as it is seen in ECL. All ECL transistors 30:02.640 --> 30:09.640 are fabricated in this manner. So, let me try to outline the steps in this ECL transistor. 30:12.110 --> 30:19.110 You remember, in a conventional transistor we started out with a p-type substrate. We 30:22.159 --> 30:29.159 had an n plus buried layer and then, we had an n epitaxial layer and we have done LOCOS. 30:36.830 --> 30:43.830 This is actually my n region and then I have the p region for the base. I have the n epitaxial 30:54.070 --> 31:01.070 region and then I have doped p. So far so good; so far nothing has changed, so far my 31:04.049 --> 31:10.990 ECL transistor looks exactly the same as the conventional transistor you have already discussed. 31:10.990 --> 31:17.990 Now, my first step is to define the extrinsic base, right. I have doped the intrinsic base. 31:20.919 --> 31:27.690 This doping is determined by the gain considerations, by the Gummel number; you have decided how 31:27.690 --> 31:34.690 much total charge to put in the base, fine. Now, next step is how to obtain the extrinsic 31:35.080 --> 31:40.870 base and how to have it self-aligned with the emitter. So as the first step you are 31:40.870 --> 31:47.870 going to deposit p plus poly and top it up with, top it up with CVD SiO 2. So, the yellow 32:09.850 --> 32:16.850 layer is .... Next, you remove it from certain portions. Fine; I have removed it from certain 33:04.059 --> 33:11.059 portions. What should I do next? I should deposit another, a second layer of CVD SiO 33:16.460 --> 33:23.460 2 and I do an anisotropic etching to partially remove the CVD SiO 2 layer. So, what do I 33:32.220 --> 33:34.789 have? I want to remove it from here. 33:34.789 --> 33:41.789 However, the side walls are retained and I remove it from here. In a way analogous to 34:00.299 --> 34:07.299 my self-aligned I-square L design, I have retained the side walls of the CVD SiO 2 and 34:09.419 --> 34:16.419 removed it from everywhere else. That is the second layer of CVD SiO 2 is retained only 34:16.460 --> 34:23.460 at the side walls and removed from everywhere else, agreed. 34:24.440 --> 34:31.440 Now, all I have to do is to deposit n plus poly all over and then remove it from certain 34:38.070 --> 34:45.070 region, so that it is retained only here. What do I do next? A thermal annealing and 34:57.460 --> 35:04.460 then, what do I have? We have .... 35:24.290 --> 35:29.880 This is my emitter; I am using a poly emitter. I have a shallow junction and also I retain 35:29.880 --> 35:36.530 the n plus poly. So, this composite layer can be used as my emitter and you see, look 35:36.530 --> 35:43.530 at the p plus extrinsic base. They are self-aligned to the emitter, separated by this spacer layer. 35:46.720 --> 35:51.180 Without this spacer layer, now you understand the importance of the spacer, without the 35:51.180 --> 35:55.720 spacer, I should have a p plus n plus junction. 35:55.720 --> 36:02.720 This spacer layer actually gives me an extrinsic base self-aligned to the emitter. This is 36:04.190 --> 36:11.190 the self-aligned poly emitter transistor with poly extrinsic base and you can take your 36:15.820 --> 36:22.820 base contact anywhere from this poly line. You do not have to have separate space for 36:25.740 --> 36:32.740 base contact; you can take it directly from this line, take it out somewhere there, right. 36:33.180 --> 36:39.589 You do not need ...., this is automatically aligned to your extrinsic base, this poly 36:39.589 --> 36:46.089 layer. So, this p plus poly layer itself is going to serve as your base contact. Considerable 36:46.089 --> 36:53.089 area saving, you have all your requirements - you have reduced the extrinsic base resistance, 36:54.200 --> 36:59.240 you have aligned, self-aligned the extrinsic base to the emitter, you have realized your 36:59.240 --> 37:00.930 poly emitter transistor. 37:00.930 --> 37:07.930 The crucial step in this self-aligned technology is realization of this spacer. This spacer 37:11.560 --> 37:18.560 must be thick enough, wide enough so as to separate the emitter and the extrinsic base. 37:18.570 --> 37:24.820 At the same time, it should not be too wide. In that case you are going to have an increase 37:24.820 --> 37:31.820 in the base resistance. So, you have to control the width of this spacer layer; the spacer 37:33.490 --> 37:40.490 layer, the side wall, the spacer side wall you have to control it very accurately. That 37:41.460 --> 37:48.460 is the most critical step. So, you can also have a variation of the same theme, you know. 37:48.590 --> 37:55.470 ..... you could do is, in this case we had deposited CVD silicon dioxide. Instead of 37:55.470 --> 38:02.470 that, you could have an undoped poly layer deposited, so that your spacer is not made 38:02.710 --> 38:09.710 of CVD SiO 2, but it is made of undoped poly and later on, you could oxidize this undoped 38:10.880 --> 38:11.490 poly. 38:11.490 --> 38:18.490 What are the advantages? You know that when silicon is oxidized, its width actually increases. 38:20.070 --> 38:27.070 So, you could actually have a very thin layer of poly spacer that would increase 2.2 times 38:33.060 --> 38:38.560 to give you the spacer layer, the adequate spacer layer. So, that actually offers you 38:38.560 --> 38:45.560 better control on the spacer layer thickness. Here you have to control the CVD SiO 2 thickness. 38:48.130 --> 38:55.130 There you were simply controlling the CVD poly thickness which can be made very thin 38:56.410 --> 39:03.410 and then when you oxidize it, it expands and gives you adequate spacer layer thickness. 39:03.450 --> 39:10.450 Second advantage is in this particular case, you see, your surface it has CVD SiO 2. CVD 39:12.520 --> 39:19.520 SiO 2 is not as good in quality as thermal oxide. If on the other hand, you deposit undoped 39:22.170 --> 39:28.170 poly and later on oxidize it, you are going to have a better quality thermal oxide protecting 39:28.170 --> 39:35.170 the surface. So, these are the two possible variations of the same theme. In order to 39:39.660 --> 39:45.920 have high speed transistors, you could use that. So many other variations are possible. 39:45.920 --> 39:52.920 In addition to this, you know, even for the intrinsic base you could use poly base. 39:55.599 --> 40:02.599 Now, the most important, most interesting aspect of this discussion - I have two figures 40:09.260 --> 40:16.260 here on the board. One is the self-aligned I-square L and the other is a transistor suitable 40:20.670 --> 40:27.670 for ECL applications. Look carefully. Don't you see that they share a number of steps? 40:36.000 --> 40:43.000 For example, this side wall spacer layer. I have a very similar step here, when I wanted 40:46.920 --> 40:53.920 to protect the n collectors from the base contact; same thing I had to do actually. 40:58.980 --> 41:05.980 This base p actually could be shared with these p's; they can be done in the same process 41:06.420 --> 41:13.420 steps. I could use this portion of the circuit in order to realize my I-square L, yes? What 41:24.010 --> 41:31.010 I am trying to drive at is this. That therefore, I can think of a process flow which will incorporate 41:32.760 --> 41:39.760 both ECL and I-square L circuits in the same chip, because you can see that the self-aligned 41:42.050 --> 41:49.050 I-square L has a lot of steps in common with the high speed transistor, high speed poly 41:49.369 --> 41:56.369 emitter transistor. Many of the steps, you see for example, this poly deposition could 41:58.240 --> 42:05.240 be shared with this poly deposition, right. So, now you can think of a circuit which can 42:12.480 --> 42:19.480 house both I-square L and ECL. What is the advantage? See, ECL circuits are high speed, 42:23.430 --> 42:30.430 high speed circuits; I-square L is high density. So, you can have a circuit in which you can 42:31.079 --> 42:38.079 try to achieve a combination of both. You see, you do not want, you may not need the 42:38.270 --> 42:45.270 entire circuit to be very fast. You only want to hasten up certain bottle necks. So, in 42:45.710 --> 42:52.710 those bottle necks you put ECL, which will speed up. In the other portions, you probable 42:54.780 --> 43:01.780 do not need such high speed, you need high density; you use I-square L circuit for that. 43:02.700 --> 43:09.700 So, this is actually a very important technical, technological approach today. That is instead 43:09.950 --> 43:16.950 of having a particular type of logic circuit, ECL or I-square L, we can have a combination, 43:18.910 --> 43:25.010 so as to suit the various needs of my circuitry, right. 43:25.010 --> 43:31.060 As the circuit becomes more and more complex, you have, you would see that certain regions 43:31.060 --> 43:38.060 is holding up the operation. I need high speed blocks for those certain regions. Other regions 43:39.770 --> 43:46.770 I need to have high density, low power dissipation. I-square L will answer admirably for that. 43:47.310 --> 43:54.310 So, more and more the approach is like this, if we can combine more than one technology 43:54.530 --> 44:01.530 in the same chip and that reaches its culminations when we can combine both the bipolar junction 44:03.690 --> 44:10.690 transistor and a MOS transistor, as happens in a biMOS technology. That is the final merger 44:12.740 --> 44:18.819 when we can combine both the bipolar junction transistor as well as MOS technology. Here 44:18.819 --> 44:24.630 what we are doing is we are trying to combine two bipolar logic - I-square L and ECL and 44:24.630 --> 44:27.520 we see that that is possible. 44:27.520 --> 44:34.520 Next, we will go on to MOS technology. We will see how with more and more demands on 44:36.599 --> 44:43.089 the MOS technology, the MOS technology begins to approach the bipolar junction process that 44:43.089 --> 44:50.089 is a number of steps in a CMOS process flow is identical to what we normally we need for 44:51.190 --> 44:58.190 bipolar junction transistor and then thereby we bring about a merger of the two technologies 44:58.260 --> 45:05.260 which is the biMOS technology or biCMOS technology. So, this is as much as I am going to discuss 45:08.930 --> 45:14.940 right now, about the bipolar junction transistor technology. In the next class we start with 45:14.940 --> 45:21.310 the MOS technology. First we take up NMOS technology, because NMOS was the prevalent 45:21.310 --> 45:28.040 MOS technology sometime back, till sometime back, 10 - 15 years back and now it is CMOS 45:28.040 --> 45:35.040 technology which has taken over from NMOS, because primarily of its low power dissipation 45:35.780 --> 45:42.440 and also because of the newer CMOS logic, the domino CMOS logic, whereby we can increase 45:42.440 --> 45:48.180 the packing density of CMOS also to a large extent. Previously CMOS used to suffer a little 45:48.180 --> 45:55.180 in comparison with NMOS, because you needed both PMOS and NMOS and as many p mass as there 45:55.339 --> 45:55.710 are NMOS. 45:55.710 --> 46:00.740 The packing density used to suffer a bit, but now using the domino CMOS logic, we have 46:00.740 --> 46:06.339 changed all that, right. Still you need PMOS and NMOS, but not in equivalent numbers, right. 46:06.339 --> 46:12.630 So, the packing density has improved a lot and CMOS of course, it always holds the trump 46:12.630 --> 46:19.630 card that its power dissipation is the minimum. That is because in a CMOS technology, one 46:20.319 --> 46:27.010 of the transistors is always OFF; whether it is in logic zero state or in logic one 46:27.010 --> 46:32.510 state, one of the transistors is always OFF. So, at steady state, power dissipation is 46:32.510 --> 46:39.510 nil. Only when the transition is occurring from 0 to 1 or 1 to 0, only in that case, 46:40.200 --> 46:45.180 momentarily for a very short time, both the transistors will be ON and we will have power 46:45.180 --> 46:51.710 dissipation. So, the power dissipation of a CMOS circuit is actually its secret of success. 46:51.710 --> 46:58.040 You can put in a large number of transistors in a chip without having to bother about the 46:58.040 --> 47:05.040 power dissipation problem. That is what we are going to do next. We are going to discuss 47:05.250 --> 47:12.250 the NMOS technology, then the CMOS technology; then, we will see how CMOS technology is gradually 47:12.250 --> 47:19.250 approaching the bipolar junction transistor technology and how we can pack both in the 47:33.240 --> 47:40.240 same chip.